The present application relates to semiconductor technology. More particularly, the present application relates to methods of forming a semiconductor structure including at least one contact structure containing a voidless contact metal structure located within a contact opening. The present application also relates to a semiconductor structure including at least one contact structure that can be formed by the methods of the present application.
In the field of semiconductor technology, it is well known to form contact metal structures within a dielectric material that contact one or more conductive regions of an underlying substrate. In one example, the one or more conductive regions may be a source region and/or a drain region that is formed in a semiconductor material, and/or a topmost portion of a gate electrode of a field effect transistor.
The formation of contact metal structures is a considerable challenge as the integration density of semiconductor devices is increased as a consequence of technology scaling. In one example, it is becoming extremely difficult to provide contact metal structures that do not contain any voids and/or keyholes. The presence of voids and/or keyholes within a contact metal structure may cause unwanted yield degradation.
In another example, and with the dimensions shrinking between the contact area (CA) and the gate structure (PC), the parasitic capacitance between the CA and PC will have a negative impact on the dynamic performance of the semiconductor device.
In view of the above, there is a need to provide new and improved contact metal structures that avoid the problems mentioned with prior art contact metal structures.